Ensuring DDR4 Electrical Performance at Intended Data-Rate
Published : 27-05-2020 - Duration : 00:44:00 - Like : 167 - Dislike : 0
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OVERVIEW DDR interfaces have many signal integrity and timing requirements that need to be guaranteed between multiple signal groups. Conformance to the requirements should be verified before a board is fabricated to reduce the chance of prototype spins. Traditionally, designers have relied on dedicated SI experts to perform this task, or laid out boards based on manufacturer’s guidelines and skipped post-route verification entirely, hoping to avoid problems in the lab. Increasing data rates h
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